1. Field of the Invention
The present invention relates to a logic circuit, and more specifically to a logic circuit suitably applicable to an arithmetic circuit using MOS transistors, which can be operated at high speed and low power consumption, while decreasing the circuit area thereof.
2. Description of the Prior Art
It has been so far well known that an asynchronous logic circuit for outputting an arithmetic operation completion signal definitely by using dynamic circuits can execute arithmetic operation at a speed higher than that of the logic circuit using static circuits. An example of the asynchronous logic circuit is disclosed by a document [A Zero-Overhead Self-Timed 160-ns 54-b CMOS Divider] by T. E. Williams et al., (IEEE J. of Solid-State Circuits, Vol. 26, No. 11, pp. 1651 to 1661 (Nov. 1991).
FIG. 18 shows a schematic block diagram showing the dynamic type asynchronous logical gate. In this asynchronous logical gate, when a reset signal is applied to two resetting transistors T.sub.A and T.sub.B, respectively, since two nodes X and XB are precharged, two circuit outputs Y and YB are reset to logical 0 via two inverters I.sub.A and I.sub.B, so that this status is defined as an incompletion status of arithmetic operation. After this reset signal has been removed, when input signals are given to two n-channel pull-down networks N.sub.A and N.sub.B each composed of n-channel transistors, any one of the nodes X and XB precharged by the reset signal is discharged to the logic 0 through any one of the two n-channel pull-down networks. As a result, since any one of the outputs Y and YB changes to logic 1, the arithmetic operation is completed.
Therefore, when a two-input logical sum circuit is connected to the outputs Y and YB, if the output of the logical sum circuit changes to 1, it is possible to indicate the completion of the arithmetic operation definitely. Further, when the arithmetic operation has not been completed yet, since the two outputs Y and YB are both 0, even if these output signals are inputted to a succeeding-stage n-channel network (not shown), this n-channel network will not operate until any one of the outputs Y and YB changes to 1.
In other words, in the arithmetic circuit obtained by connecting a plurality of the arithmetic circuits in cascade as described above, since the valid arithmetic outputs can indicate the completion of the arithmetic operation and a start of operation of the succeeding stage n-channel network at the same time, the operation of the succeeding stage can be started simultaneously when the arithmetic operation of the present stage is completed, with the result that it is possible to realize an extremely high speed arithmetic circuit. In the case of the above-mentioned document, a plurality of the arithmetic circuits are connected in a ring-shape on the basis of the above-mentioned feature, and further a reset signal is supplied to the circuit by use of an arithmetic completion signal appropriately, in order to realize a high speed arithmetic circuit in which the processing time required for resetting is not at all needed.
However, a higher speed and a lower power consumption are both required year by year for the digital signal processor (DSP) and the microprocessor. On the other hand, conventionally, in the respective arithmetic circuits such as addition, subtraction, multiplication and division assembled in the digital signal processor or the microcomputer, the operation speeds of a division circuit and a square root arithmetic circuit for calculating data in accordance with an algorithm the same as that of the division circuit are particularly slow. In the practical arithmetic processing, however, since the number of times required for these arithmetic operations is relatively small, the processing speed of the whole processor is not often limited by the slow operation speeds of these division and the square root arithmetic circuits. Recently, however, with the rapid advance of image data processing, there exists a need of executing the division operation and the square root arithmetic operation at frequency much higher than is conventional, as with the case of the three-dimensional data processing, for instance. As the example of these processing, there are the square root operation for calculating a distance between two points in a three-dimensional space and the division operation for executing normalizing arithmetic operation of the distance thus obtained. Therefore, there exists a need of a logic circuit which can execute both the division and square root arithmetic processing at a high speed and low power consumption.
In the case of the prior art circuit as shown in FIG. 18, however, although the arithmetic operation speed is high, whenever the arithmetic operation is executed once, since the outputs Y and YB must be returned to 0 by resetting, even if the input signals for providing the same arithmetic results are given continuously, it is necessary to execute the same arithmetic operation again, with the result that the power consumption increases.
In contrast with this, in the case of the static circuits so far used widely, although the arithmetic operation speed is slow, as far as the input signals do not change, since the output signals are not at all changed, the power consumption at this interval is almost zero (although leak current exists). Further, in the case of the circuit as shown in FIG. 18, although two wires connected to the two outputs Y and YB are necessary in order to represent one-bit logical output signal, since only a single wire is necessary for the static circuit, it is possible to reduce the number of the wires.
As described above, in the case of the asynchronous logic circuit composed of dynamic circuits, although a high speed operation can be made, there exists a disadvantage such that the power consumption is large and the wiring quantity increases.
Therefore, it may be considered to form the synchronous circuit in such a way that static circuits are used only at the circuit portion where high speed operation is not required. In this case, however, when the signals of the static circuits are inputted to the dynamic asynchronous circuits, additional converter circuits are required, which can convert the output of the synchronous circuit to a signal form required on the dynamic circuit side. Therefore, even when both the circuits are simply combined with each other, the overhead of the hardware and the loss of the arithmetic time both increase, with the result that the merits of combining the synchronous circuits are canceled with each other.